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edi2cg272128v 1 white electronic designs corporation ? (508) 366-5151 ?www.whiteedc.com august 2000 rev.0 eco#13088 the edi2cg272128vxxd1 is a synchronous/synchronous burst sram, 72 position dimm (144 contacts) module, small outline. the module contains four (4) synchronous burst ram devices, packaged in the industry standard jedec 14mmx20mm tqfp placed on a multilayer fr4 substrate. the module architecture is defined as a sync/sync burst, flow-through, with support for either linear or sequential burst. this module provides high performance, 2-1-1-1 accesses when used in burst mode, and used as a synchronous only mode, provides a high performance cost advantage over bicmos aysnchronous device architectures. synchronous only operations are performed via strapping adsc low, and adsp / adv high, which provides for ultra fast accesses in read mode while providing for internally self-timed early writes. synchronous/synchronous burst operations are in relation to an externally supplied clock, registered address, registered global write, registered enables as well as an asynchronous output enable. this module has been defined for quad word access in both read and write operations. features 2x128kx72 synchronous, synchronous burst flow-through architecture linear and sequential burst support via mode pin access speed(s): t khqv = 8.5, 9, 12, 15ns clock controlled registered bank enables (e 1 , e 2 ) clock controlled registered address clock controlled registered global write (gw) aysnchronous output enable (g) internally self-timed write individual bank sleep mode enables (zz 1 , zz 2 ) gold lead finish 3.3v 10% operation common data i/o high capacitance (30pf) drive, at rated access speed single total array clock multiple vcc and gnd 2x128kx72, 3.3v sync/sync burst flow-through
edi2cg272128v 2 white electronic designs corporation ? (508) 366-5151 ?www.whiteedc.com august 2000 rev.0 eco#13088 fig. 1 functional block diagram pin configuration dq 0-63 input/output bus dqp 0-7 parity bits a 0-16 address bus e 1 , e 2 synchronous bank enables clk array clock gw synchronous global write enable g asynchronous output enable zz 1 , zz 2 blank sleep mode enables vcc 3.3v power supply vss ground nc no connect pin names pin pin pin pin function function function function 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 v ss v ss a 0 rfu a 16 a 1 a 2 a 15 a 14 a 3 a 4 a 13 a 12 a 5 a 6 a 10 a 8 v cc g gw adsp mode v ss e 1 v cc dq 0 dq 1 dq 2 dq 3 v ss zz 1 v cc dq 8 dq 9 dq 10 dq 11 v ss e 2 v cc dq 16 dq 17 dq 18 dq 19 v ss zz 2 v cc dq 24 dq 25 dq 26 dq 27 v ss rfu v cc dq 32 dq 33 dq 34 dq 35 v ss rfu v cc dq 40 dq 41 dq 42 dq 43 v ss rfu v cc dq 48 dq 49 dq 50 dq 51 v ss rfu v cc dq 56 dq 57 dq 58 dq 59 v ss v ss dq 60 dq 61 dq 62 dq 63 v cc dqp 7 v ss dq 52 dq 53 dq 54 dq 55 v cc dqp 6 v ss dq 44 dq 45 dq 46 dq 47 v cc dqp 5 v ss dq 36 dq 37 dq 38 dq 39 v cc dqp 4 v ss dq 28 dq 29 dq 30 dq 31 v cc dqp 3 v ss dq 20 dq 21 dq 22 dq 23 v cc dqp 2 v ss dq 12 dq 13 dq 14 dq 15 v cc dqp 1 v ss dq 4 dq 5 dq 6 dq 7 v cc dqp 0 v ss clk adsc adv rfu v cc a 9 a 7 a 11 1 2 3 4 5 6 7 8 9 adsc adsp adv clk g gw a 0-16 adsc adsp adv clk g gw dq e zz e 1 zz 1 adsc adsp adv clk g gw dq e zz adsc adsp adv clk g gw dq e zz adsc adsp adv clk g gw dq e zz u1 u2 u3 u4 e 2 zz 2 dq 0-31 dqp 0-3 dq 32-63 dqp 4-7 dq 32-63 dqp 4-7 dq 0-31 dqp 0-3 pin symbols
edi2cg272128v 3 white electronic designs corporation ? (508) 366-5151 ?www.whiteedc.com august 2000 rev.0 eco#13088 pin descriptions dimm pins symbol type description 3, 6, 10, 11, 14, 15, a 0-16 input addresses: these inputs are registered and must meet the setup and hold times around the rising edge of clk. 18, 19, 20, 17, 16, synchronous the burst counter generates internal addresses associated with a0 and a1, during burst and wait c ycle. 13, 12, 9, 8, 3, 5 25 gw input global write: this active low input allows a full 72-bit write to occur independent of the bwe and bwx lines synchronous and must meet the setup and hold times around the rising edge of clk. 30 clk input clock: this signal registers the addresses, data, chip enables, write control and burst control inputs on its rising edge. synchronous all synchronous inputs must meet setup and hold times around the clocks rising edge. 33, 61 e 1 , e 2 input bank enables: these active low inputs are used to enable each individual bank and to gate adsp synchronous 23 g input output enable: this active low asynchronous input enables the data output drivers. 26 adv input address status processor: this active low input is used to control the internal burst counter. a high on this pin synchronous generates wait cycle (no address advance). 27 adsp input address status processor: this active low input, along with el and eh being low, causes a new externaladdress synchronous to be registered and a read cycle is initiated using the new address. 28 adsc input address status controller: this active low input causes device to be de-selected or selected along with new externa l synchronous address to be registered. a read or write cycle is initiated depending upon write control inputs. 29 mode input static mode: this input selects the burst sequence. a low on this pin selects linear burst. a nc or high on this pin selects interleaved burst. 47, 75 zz 1 , zz 2 input snooze: these active high inputs put the individual banks in low power consumption standby mode. for normal asynchronous operation, this input has to be either low or nc (no connect). various dq 0-63 input/output data inputs/outputs: first byte is dq 0-7 , second byte is dq 8-15 , third byte is dq 16-23 , fourth byte is dq 24-31 , fifth byte is dq 32-39 , sixth byte is dq 40-47 , seventh byte is dq 48-55 and the eight byte is dq 56-64 . 34, 48, 62, 76, dqp 0-7 input/output parity inputs/outputs: dqp 0 is parity bit for dq 0-7 . dqp 1 is parity bit for dq 8-15 . dqp 2 is parity bit for dq 16-23 . dqp 3 is 90, 104, 118, 132 parity bit for dq 24-31 . dqp 4 is parity bit for dq 32-39 . dqp 5 is parity bit for dq 40-47 . dqp 6 is parity bit for dq 48-55 . dqp 7 is parity bit for dq 56-64 and dqp 7 . in order to use the device configured as a 128k x 64, the parity bits need to be tied to vss through a 10k ohm resistor. various vcc supply core power supply: +3.3v -5%/+10% various vss ground ground
edi2cg272128v 4 white electronic designs corporation ? (508) 366-5151 ?www.whiteedc.com august 2000 rev.0 eco#13088 synchronous burst - truth table operation e1 e2 adsp adsc adv gw g clk dq addr. used deselected cycle, power down; bank 1 h x x l x x x l-h high-z none deselected cycle, power down; bank 2 x h x l x x x l-h high-z none read cycle, begin burst; bank 1 l h l x x x l l-h q external read cycle, begin burst; bank 1 l h l x x x h l-h high-z external read cycle, begin burst; bank 2 h l l x x x l l-h q external read cycle, begin burst; bank 2 h l l x x x h l-h high-z external write cycle, begin burst; bank 1 l h h l x l x l-h d external write cycle, begin burst; bank 2 h l h l x l x l-h d external read cycle, begin burst; bank 1 l h h l x h l l-h q external read cycle, begin burst; bank 1 l h h l x h h l-h high-z external read cycle, begin burst; bank 2 h l h l x h l l-h q external read cycle, begin burst; bank 2 h l h l x h h l-h high-z external read cycle, continue burst; bank 1 x h x h l h l l-h q next read cycle, continue burst; bank 1 x h x h l h h l-h high-z next read cycle, continue burst; bank 2 h x x h l h l l-h q next read cycle, continue burst; bank 2 h x x h l h h l-h high-z next read cycle, continue burst; bank 1 h h x h l h l l-h q next read cycle, continue burst; bank 1 h h x h l h h l-h high-z next read cycle, continue burst; bank 2 h h x h l h l l-h q next read cycle, continue burst; bank 2 h h x h l h h l-h high-z next write cycle, continue burst; bank 1 x h h h l l x l-h d next write cycle, continue burst; bank 1 h h x h l l x l-h d next write cycle, continue burst; bank 2 h x h h l l x l-h d next write cycle, continue burst; bank 2 h h x h l l x l-h d next read cycle, suspend burst; bank 1 x h h h h h l l-h q current read cycle, suspend burst; bank 1 x h h h h h h l-h high-z current read cycle, suspend burst; bank 2 h x h h h h l l-h q current read cycle, suspend burst; bank 2 h x h h h h h l-h high-z current read cycle, suspend burst; bank 1 h h x h h h l l-h q current read cycle, suspend burst; bank 1 h h x h h h h l-h high-z current read cycle, suspend burst; bank 2 h h x h h h l l-h q current read cycle, suspend burst; bank 2 h h x h h h h l-h high-z current write cycle, suspend burst; bank 1 x h h h h l x l-h d current write cycle, suspend burst; bank 1 h h x h h l x l-h d current write cycle, suspend burst; bank 2 h x h h h l x l-h d current write cycle, suspend burst; bank 2 h h x h h l x l-h d current
edi2cg272128v 5 white electronic designs corporation ? (508) 366-5151 ?www.whiteedc.com august 2000 rev.0 eco#13088 dc electrical characteristics - read cycle recommended dc operating conditions absolute maximum ratings* *stress greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in operational sections of this specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. voltage on vcc relative to vss -0.5v to +4.6v vin -0.5v to vcc +0.5v storage temperature -55 c to +125 c operating temperature (commercial) 0 c to +70 c operating temperature (industrial) -40 c to +85 c short circuit output current 10 ma parameter sym min typ max units supply voltage v cc 3.14 3.3 3.6 v supply voltage v ss 0.0 0.0 0.0 v input high v ih 2.0 3.0 v cc +0.3 v input low v il -0.3 0.0 0.8 v input leakage il i -2 1 2 a output leakage ilo -2 1 2 a max description symbol typ 8.5 9 12 15 units power supply current icc 1 1.55 2.2 2.1 2.1 2.0 a power supply current icc 750 1.5 1.5 1.0 1.0 a device selected, no operation snooze mode icc zz 150 200 200 200 200 ma cmos standby icc3 400 600 600 600 600 ma clock running-deselect icck 600 1.0 1.0 0.75 0.75 a synchronous only - truth table operation e1 e2 gw g zz clk dq synchronous write-bank 1 l h l h l high-z synchronous read-bank 1 l h h l l synchronous write-bank 2 h l l h l high-z synchronous read-bank 2 h l h l l synchronous write-bank 3 h h l h l high-z synchronous read-bank 3 h h h l l synchronous write-bank 4 h h l h l high-z synchronous read-bank 4 h h h l l snooze mode xxxxh x high-z ac test circuit ac test conditions 50 ? vt = 1.5v i/o z0 = 50 ? z0 = 50 ? parameter i/o unit input pulse levels v ss to 3.0 v input and output timing levels 1.25 v output test equivalencies see figure, at left fig. 2 ac output load equivalent 1.25v
edi2cg272128v 6 white electronic designs corporation ? (508) 366-5151 ?www.whiteedc.com august 2000 rev.0 eco#13088 fig. 3 synchronous only read cycle read cycle timing parameters *tbd 8.5ns 9ns 12ns 15ns description sym min max min max min max min max units clock cycle time t khkh **10 12 15 ns clock high time t khkl ** 4 5 5 ns clock low time t klkh ** 4 5 5 ns clock to output valid t khqv ** 9 10 12ns clock to output invalid t khqx1 ** 3 3 3 ns clock to output low-z t khqx ** 2 2 2 ns output enable to output valid t glqv ** 4 4 5ns output enable to output low-z t glqx ** 0 0 0 ns output enable to output high-z t ghqz ** 4 4 5ns address setup t avkh * * 2.5 2.5 2.5 ns bank enable setup t evkh * * 2.5 2.5 2.5 ns address hold t khax * * 1.0 1.0 1.0 ns bank enable hold t khex * * 1.0 1.0 1.0 ns first second third fourth address address address address (external) (internal) (internal) (internal) a..a00 a..a01 a..a10 a..a11 a..a01 a..a00 a..a11 a..a10 a..a10 a..a11 a..a00 a..a01 a..a11 a..a10 a..a01 a..a00 burst address table (mode = v ss ) burst address table (mode = nc/v cc ) first second third fourth address address address address (external) (internal) (internal) (internal) a..a00 a..a01 a..a10 a..a11 a..a01 a..a10 a..a11 a..a00 a..a10 a..a11 a..a00 a..a01 a..a11 a..a00 a..a01 a..a10 t khqx dq read cycle q(addr 1) q(addr 1) q(addr 2) t khqz gw g addr ex clk t khqv addr 1 addr 2 addr 1 t khkh t klkh t khkl t glqx back to back read t khqx1 t glqv t khax t avkh
edi2cg272128v 7 white electronic designs corporation ? (508) 366-5151 ?www.whiteedc.com august 2000 rev.0 eco#13088 fig. 4 synchronous-burst read cycle t scvkh t khscx t ghqx burst read cycle t evkh t khex read cycle t glqv t glqx t khqx dq g ex adv bwx, gw t ghqz t khkh t khkl t spvkh t khspx t avkh t khax adsp addr adsc clk t klkh t khqv t khqx t avvkh t khavx
edi2cg272128v 8 white electronic designs corporation ? (508) 366-5151 ?www.whiteedc.com august 2000 rev.0 eco#13088 fig. 5 synchronous (non-burst) write cycle write cycle timing parameters 8.5ns 9ns 12ns 15ns description sym min max min max min max min max units clock cycle time t khkh 91215ns clock high time t khkl 455ns clock low time t klkh 455ns address setup t avkh 2.5 2.5 2.5 ns address hold t khax 1.0 1.0 1.0 ns bank enable setup t evkh 2.5 2.5 2.5 ns bank enable hold t khex 1.0 1.0 1.0 ns global write enable setup t wvkh 2.5 2.5 2.5 ns global write enable hold t khwx 1.0 1.0 1.0 ns data setup t dvkh 2.5 2.5 2.5 ns data hold t khdx 1.0 1.0 1.0 ns t ghkh t gwlkh t avkh t dvkh write cycle g gw addr clk ex addr 1 addr 1 addr 2 t klkh t khkh t khkl back to back writes t khgh t khdx t khgwh t khax dq
edi2cg272128v 9 white electronic designs corporation ? (508) 366-5151 ?www.whiteedc.com august 2000 rev.0 eco#13088 fig. 6 synchronous-burst write cycle burst - late write- cycle t evkh t khex early write cycle t dvkh t khqx dq g ex adv bwx, gw t khkh t khkl t avkh t khax adsp addr adsc clk t klkh t khqx t avvkh t khavx
edi2cg272128v 10 white electronic designs corporation ? (508) 366-5151 ?www.whiteedc.com august 2000 rev.0 eco#13088 fig. 7 synchronous (non-burst) read/write cycle write cycle t dvkh back to back cycles g controlled d (addr 2) gw dq q (addr 1) read cycle t khqx t avkh g addr ex clk t khqv addr 1 addr 2 t khdx t khkh t klkh t khkl t khdx
edi2cg272128v 11 white electronic designs corporation ? (508) 366-5151 ?www.whiteedc.com august 2000 rev.0 eco#13088 package description: 144 lead small outline dimm ordering information part number organization voltage speed (ns) package edi2cg272128v85d1* 2x128kx72 3.3 8.5 144 small outline dimm EDI2CG272128V9D1* 2x128kx72 3.3 9 144 small outline dimm edi2cg272128v12d1 2x128kx72 3.3 12 144 small outline dimm edi2cg272128v15d1 2x128kx72 3.3 15 144 small outline dimm *consult factory for availability package no. 409 2.667 max. 1.000 max. 0.788 0.157 0.181 typ 0.913 1.291 1.112 1.490 0.175 max. u1 r3 r5 r13 r7 r11 r1 u3 r9 r17 r18 r15 p1 all dimensions are in inches

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